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ISL59531
Data Sheet March 21, 2006 FN6251.0
PRELIMINARY
16x16 Video Crosspoint with Differential Inputs
The ISL59531 is a 16x16 integrated video crosspoint switch matrix with differential input and On-Screen Display (OSD) insertion. The ISL59531 is ideal for routing video signals in security and video-on-demand systems. This device operates from a single +5V supply. Any output of the 16 video inputs cable can be switched to any of the 16 outputs. OSD information can be inserted into any output through an internal, dedicated fast 2:1 mux (15ns switching times) located before the output buffer. Also, any input can be broadcast to all 16 outputs. Each output can be tri-stated and its gain set to +1 or +2 through the SPI interface. The ISL59531 offers a -3dB signal bandwidth of 320MHz. The differential gain and differential phase of 0.025%, along with 0.1dB flatness out to 50MHz, making the ISL59531 suitable for many video applications. The switch matrix configuration and output buffer gain are programmed through an SPI/QSPITM-compatible three-wire serial interface. The ISL59531 interface is set up to facilitate both fast updates and initialization. On power-up, all outputs are initialized in the disabled state to avoid output conflicts within the user system. The ISL59531 has single-supply signal operation. It can accommodate input common mode voltages from 0V to 3.5V and 0V to 4V at the outputs. The ISL59531 is available in a 356-pin BGA package and specified over an extended -40C to +85C temperature range. The ISL59530 is a single-ended input version of this device. For capacitor-coupled applications, the ISL59530 inputs include a clamp circuit that restores the input level to an externally applied reference.
Features
* 16x16 non-blocking switch with differential inputs and outputs * Operates from a single +5V supply * Output gain switchable +1 or +2 * SPI digital interface * Tri-state output * -90dB Isolation at 6MHz * 0.025%/0.05 dG/dP * Pb-free plus anneal available (RoHS compliant)
Applications
* Security camera switching * RGB routing * HDTV routing
Ordering Information
PART NUMBER ISL59531IKZ (See Note) TAPE & REEL PACKAGE 356-Pin BGA (Pb-free) PKG. DWG. # V356.27x27
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59531 Pinout
ISL59531 (356-PIN BGA) TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A
In12 Inb12 In13 Inb13 In14 Inb14 In15 Inb15 Over15 Out15 Vover15 In11 Inb11 Vlogic Vs Vs In10 Inb10 Sout In9 Inb9 Reset Senb In8 Inb8 Clock Sdi In7 Inb7 Ref Vs Vs Vs Vs Vs Vs Vs Vs In6 Inb6 Vs Vs In5 Inb5 Vs Vs In4 Inb4 Inb3 In3 Inb2 In2 Vs Vs Vs Vs Vs Vs Vs Vs Vover1 Over1 Out1 Vs Vs Vover2 Out2 Over2 Vs Vs Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Vs Vs Vs Vs Vs Vs Vs Vs Over14 Out14 Vover14 Vs Vs Out13 Over13 Vover13 Vs Vs Out12
B
Over12
C
Vover12
D
Vs Vover11 Out11 Over11
E
Vs
F
Vs Vover10Out10 Over10
G
Vs
H
Vs Vover9 Over9 Out9
J
Vs
K
Vs Vover8 Over8 Out8
L
Vs
M
Vs Vover7 Out7 Over7
N
Vs
P
Vs Vover6 Out6 Over6
R
Vs
T
Vs Vover5 Over5 Out5
U V
Spare1 Spare0 Inb1 In1 Inb0 In0 Diode Vover0 Over0 Out0 Vover3 Out3 Vover4 Over4 Out4
W Y
Over3
= Empty location (unpopulated) = Ballgrid Pad name "GND" is the same as package or ball name "ground" or "G" Pad name "VS" is the same as package or ball name "power" or "P" Pad X, Y is from pad center. All pads are 70 by 70
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FN6251.0 March 21, 2006
ISL59531
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VS and GND. . . . . . . . . . . . . . . . . . . . 5.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 40mA Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER VS VD AV Supply Range Digital Supply Gain
VS = 5V CONDITION MIN 4.5 Establishes serial output high level AV = 1, RL = 500 AV= 2, RL = 150 1.2 0.97 1.94 -1.5 1 2 1 0.5 0 0 -10 AV = 1 AV = 2 -25 -70 60 25 -5 0 0 100 35 80 Enabled, all outputs enable, no load current Enable, all outputs disable, no load current Disabled Supply current per output channel 312 140 0.8 7 1.1 375 TYP MAX 5.5 5.5 1.03 2.06 1.5 1.0 3.5 4.0 0 25 70 UNIT V V V/V V/V % % V V A mV mV mA mA dB mA mA mA mA
DESCRIPTION
GM
Gain Matching (to average of all other outputs) Input Voltage Range Output Voltage Range Input Bias Current Output Offset Voltage
AV = 1 AV = 2 AV = 1 AV = 2, RL = 150
VIN VOUT IB VOS
IOUT
Output Current
Sourcing, RL = 10 to GND Sinking, RL to 2.5V
PSRR IS
Power Supply Rejection Ratio Supply Current
AC Electrical Specifications
PARAMETER BW -3dB BW 0.1dB SR TS Glitch Tover dG dP Xt VN DESCRIPTION 3dB Bandwidth 0.1dB Bandwidth Slew Rate Settling Time to 0.1% Switching Glitch, Peak Overlay Delay Time Diff Gain Diff Phase Hostile Crosstalk Input Noise Voltage CONDITION VOUT = 200mVP-P, AV = 2 VOUT = 200mVP-P, AV = 2 VOUT = 2VP-P, AV = 2 VOUT = 2VP-P, AV = 2 AV = 1 Beginning of output transition AV = 2, RL = 150 AV = 2, RL = 150 6MHz 360 MIN TYP 320 50 520 12 40 6 0.025 0.05 -85 42 MAX UNIT MHz MHz V/s ns mV ns %
dB nV/Hz
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FN6251.0 March 21, 2006
ISL59531 Pin Descriptions
NAME INB2 IN2 INB3 IN3 REF GND SDI VS INB4 IN4 INB5 IN5 VS GND INB6 IN6 INB7 IN7 CLOCK VS SENB GND INB8 IN8 INB9 IN9 VS GND INB10 IN10 INB11 IN11 RESET VS SOUT GND INB12 IN12 INB13 NUMBER W4 Y4 W2 Y2 M3 GND L3 VS V2 V1 T2 T1 VS GND P2 P1 M2 M1 K3 VS J3 GND K2 K1 H2 H1 VS GND F2 F1 D2 D1 H3 VS G3 GND B1 A1 B3 DESCRIPTION Complementary input Input Complementary input Input Output reference Ground Serial data input Power supply Complementary input Input Complementary input Input Power supply Ground Complementary input Input Complementary input Input Serial data clock Power supply Serial enable-inverted Ground Complementary input Input Complementary input Input Power supply Ground Complementary input Input Complementary input Input Reset input Power supply Serial data output Ground Complementary input Input Complementary input
Pin Descriptions (Continued)
NAME IN13 INPUT TEST BAR GND GND VS VS VLOGIC INB14 IN14 INB15 IN15 VSL VGL VS GND OVER15 VOVER15 OUT15 OVER14 VOVER14 OUT14 GND VS OUT13 VOVER13 OVER13 OUT12 VOVER12 OVER12 GND OUT TEST 3 VS OVER11 VOVER11 OUT11 OVER10 VOVER10 OUT10 NUMBER A3 NONE GND GND VS VS D3 B5 A5 B7 A7 VS GND VS GND A11 C11 B11 A13 C13 B13 GND VS A15 C15 B15 A17 C17 B17 GND NONE VS D20 D18 D19 F20 F18 F19 Input Manufacturing test pin - leave open Ground Ground Power supply Power supply Logic power supply for serial output driver Complementary input Input Complementary input Input Power supply Ground Power supply Ground Overlay logic control Overlay analog input Output Overlay logic control Overlay analog input Output Ground Power supply Output Overlay analog input Overlay logic control Output Overlay analog input Overlay logic control Ground Manufacturing test pin - leave open Power supply Overlay logic control Overlay analog input Output Overlay logic control Overlay analog input Output DESCRIPTION
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FN6251.0 March 21, 2006
ISL59531 Pin Descriptions (Continued)
NAME GND VS OUT9 VOVER9 OVER9 OUT8 VOVER8 OVER8 OUT TEST 2 GND VS OVER7 VOVER7 OUT7 OVER6 VOVER6 OUT6 GND VS OUT5 VOVER5 OVER5 OUT4 VOVER4 OVER4 VS OUT TEST 1 GND OVER3 VOVER3 OUT3 OVER2 VOVER2 OUT2 VS GND OUT1 VOVER1 OVER1 OUT0 NUMBER GND VS H20 H18 H19 K20 K18 K19 NONE GND VS M20 M18 M19 P20 P18 P19 GND VS T20 T18 T19 V20 V18 V19 VS NONE GND Y16 V16 W16 Y14 V14 W14 VS GND Y12 V12 W12 Y10 Ground Power supply Output Overlay analog input Overlay logic control Output Overlay analog input Overlay logic control Manufacturing test pin - leave open Ground Power supply Overlay logic control Overlay analog input Output Overlay logic control Overlay analog input Output Ground Power supply Output Overlay analog input Overlay logic control Output Overlay analog input Overlay logic control Power supply Manufacturing test pin - leave open Ground Overlay logic control Overlay analog input Output Overlay logic control Overlay analog input Output Power supply Ground Output Overlay analog input Overlay logic control Output VS GND VS GND SPARE0 SPARE1 VS GND VS GND V6 V5 DESCRIPTION
Pin Descriptions (Continued)
NAME VOVER0 OVER0 VS OUT TEST 0 GND IN0 INB0 IN1 INB1 DIODE NUMBER V10 W10 VS NONE GND Y8 W8 Y6 W6 V9 DESCRIPTION Overlay analog input Overlay logic control Power supply Manufacturing test pin - leave open Ground Input Complementary input Input Complementary input Anode of a ground-connected diode: useful for measuring die temperature Power supply Ground Power supply Ground Not assigned-do not connect Not assigned-do not connect
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FN6251.0 March 21, 2006
ISL59531 Typical Performance Curves
Vs=+5V AV = 1 RL = 100 INPUT_CH 0 OUTPUT_CH 0
15pF 10pF
VS=+5V AV = 2 RL = 100 INPUT_CH 0 OUTPUT_CH 0
15pF
10pF
4.7pF
4.7pF
0pF
0pF
FIGURE 1. FREQUENCY RESPONSE - VARIOUS CL, AV = 1, MUX MODE
FIGURE 2. FREQUENCY RESPONSE - VARIOUS CL, AV = 2, MUX MODE
VS=+5V AV = 1 CL = 0pF INPUT_CH 0 OUTPUT_CH 0
150
50
VS=+5V AV = 2 CL = 0 INPUT_CH 0 OUTPUT_CH 0
150
50
500 500 1.03k 1.03k
FIGURE 3. FREQUENCY RESPONSE - VARIOUS RL, AV = 1, MUX MODE
FIGURE 4. FREQUENCY RESPONSE - VARIOUS RL, AV = 2, MUX MODE
Overlay mode AV = 1 RL = 100 CL=0pF INPUT_CH 15 OUTPUT_CH 31
Overlay mode AV = 2 RL = 100 CL=0pF INPUT_CH 15 OUTPUT_CH 15
FIGURE 5. FREQUENCY RESPONSE - OVERLAY INPUT, AV = 1
FIGURE 6. FREQUENCY RESPONSE - OVERLAY INPUT, AV = 2
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FN6251.0 March 21, 2006
ISL59531 Typical Performance Curves (Continued)
VS=+5V AV = 1 RL = 100 INPUT_CH 0 OUTPUT_CH 0
15pF 10pF
VS=+5V AV = 2 RL = 100 INPUT_CH 0 OUTPUT_CH 0
15pF 10pF
4.7pF
4.7pF
0pF
0pF
FIGURE 7. FREQUENCY RESPONSE - VARIOUS CL, AV = 1, BROADCAST MODE
FIGURE 8. FREQUENCY RESPONSE - VARIOUS CL, AV = 2, BROADCAST MODE
VS=+5V AV = 1 CL = 0pF INPUT_CH 0 OUTPUT_CH 0
150
50
VS=+5V AV = 2 CL = 0pF INPUT_CH 0 OUTPUT_CH 0
50 150K
503
503k 1.03K
1.03k
FIGURE 9A. FREQUENCY RESPONSE - VARIOUS RL, AV = 1, BROADCAST MODE
FIGURE 10. FREQUENCY RESPONSE - VARIOUS RL, AV = 2, BROADCAST MODE
AV = 1 RL = 100 CL = 0
ADJACENT INPUT_CH14 OUTPUT_CH15
AV = 2 RL = 100 CL = 0
ADJACENT INPUT_CH14 OUTPUT_CH15
ALL HOSTILE INPUT_CH0 OUTPUT_CH31
ALL HOSTILE INPUT_CH0 OUTPUT_CH15
FIGURE 11. CROSSTALK - AV = 1
FIGURE 12. CROSSTALK - AV = 2
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FN6251.0 March 21, 2006
ISL59531 Typical Performance Curves (Continued)
THD
THD
VS=+5V AV=2 RL=100 INPUT_CH 0 OUTPUT_CH 0 FREQUENCY = 1MHz 2nd HD
2nd HD 3rd HD
VS=+5V AV=2 RL=100 INPUT_CH 0 OUTPUT_CH 0 VOP-P =2V
3rd HD
FIGURE 13. HARMONIC DISTORTION vs FREQUENCY
FIGURE 14. HARMONIC DISTORTION vs VOUT_P-P
FIGURE 15. DISABLE OUTPUT IMPEDANCE
FIGURE 16. ENABLE OUTPUT IMPEDANCE
MUX MODE AV = 1 RL = 100 INPUT_CH 15 OUTPUT_CH 15 FALL TIME 2.65ns
RISE TIME 2.35ns
MUX MODE AV = 1 RL = 100 INPUT_CH 15 OUTPUT_CH 15
FIGURE 17. RISE TIME - AV = 1
FIGURE 18. FALL TIME - AV = 1
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FN6251.0 March 21, 2006
ISL59531 Typical Performance Curves (Continued)
MUX MODE AV = 2 RL = 100 INPUT_CH 15 OUTPUT_CH 15
FALL TIME 2.35ns
RISE TIME 2.19ns
MUX MODE AV = 2 RL = 100 INPUT_CH 15 OUTPUT_CH 15
FIGURE 19. RISE TIME - AV = 2
FIGURE 20. FALL TIME - AV = 2
MUX MODE AV = 1 RL=100 INPUT_CH 15 OUTPUT_CH 15 SLEW RATE 448V/s SLEW RATE -436V/s
MUX MODE AV = 1 RL=100 INPUT_CH 15 OUTPUT_CH 15
FIGURE 21. RISING SLEW RATE - AV = 1
FIGURE 22. FALLING SLEW RATE - AV = 1
MUX MODE AV = 2 RL=100 INPUT_CH 15 OUTPUT_CH 15 SLEW RATE 531V/s
SLEW RATE -511V/s
MUX MODE AV = 2 RL=100 INPUT_CH 15 OUTPUT_CH 15
FIGURE 23. RISING SLEW RATE - AV = 2
FIGURE 24. FALLING SLEW RATE - AV = 2
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FN6251.0 March 21, 2006
ISL59531 Typical Performance Curves (Continued)
OUTPUT
OUTPUT
OVERLAY LOGIC INPUT
OVERLAY LOGIC INPUT
FIGURE 25. OVERLAY SWITCH TURN-ON DELAY TIME
FIGURE 26. OVERLAY SWITCH TURN-OFF DELAY TIME
AV = 2 RL = 150 INPUT_CH 15 OUTPUT_CH 15 OSC = 40mV
AV = 2 RL = 150 INPUT_CH 15 OUTPUT_CH 15 OSC = 40mV
FIGURE 27. DIFFERENTIAL GAIN, AV = 2
FIGURE 28. DIFFERENTIAL PHASE, AV = 2
AV = 2 RL = 150 INPUT_CH 15 OUTPUT_CH 15 OSC = 40mV
AV = 2 RL = 150 INPUT_CH 15 OUTPUT_CH 15 OSC = 40mV
FIGURE 29. DIFFERENTIAL GAIN, AV = 2
FIGURE 30. DIFFERENTIAL PHASE, AV = 2
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FN6251.0 March 21, 2006
ISL59531 Typical Performance Curves (Continued)
AV = 1 RL = 150 INPUT_CH 15 OUTPUT_CH15 OSC = 40mV
AV = 1 RL = 150 INPUT_CH 15 OUTPUT_CH 15 OSC = 40mV
FIGURE 31. DIFFERENTIAL GAIN, AV = 1
FIGURE 32. DIFFERENTIAL PHASE, AV = 1
AV = 1 RL = 150 INPUT_CH 15 OUTPUT_CH 15 OSC = 40mV
AV = 1 RL = 150 INPUT_CH 15 OUTPUT_CH 15 OSC = 40mV
FIGURE 33. DIFFERENTIAL GAIN, AV = 1
FIGURE 34. DIFFERENTIAL GAIN, AV = 1
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV
FIGURE 35. DIFFERENTIAL GAIN, AV = 2
FIGURE 36. DIFFERENTIAL PHASE, AV = 2
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FN6251.0 March 21, 2006
ISL59531 Typical Performance Curves (Continued)
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV
FIGURE 37. DIFFERENTIAL GAIN, AV = 2
FIGURE 38. DIFFERENTIAL PHASE, AV = 2
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV
FIGURE 39. DIFFERENTIAL GAIN, AV = 1
FIGURE 40. DIFFERENTIAL PHASE, AV = 1
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 15 OSC = 40mV
FIGURE 41. DIFFERENTIAL GAIN, AV = 1
FIGURE 42. DIFFERENTIAL PHASE, AV = 1
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FN6251.0 March 21, 2006
ISL59531 Typical Performance Curves (Continued)
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV
FIGURE 43. DIFFERENTIAL GAIN, OVERLAY, AV = 2
FIGURE 44. DIFFERENTIAL PHASE, OVERLAY, AV = 2
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV
FIGURE 45. DIFFERENTIAL GAIN, OVERLAY, AV = 1
FIGURE 46. DIFFERENTIAL PHASE, OVERLAY, AV = 1
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FN6251.0 March 21, 2006
ISL59531
3dB Bandwidth, MUX Mode, AV = 1, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 5 OUTPUT CHANNELS 6 7 8 9 10 11 12 13 14 15 255 244 257 264 255 253 247 253 255 241 235 223 220 211 199 193 212 217 207 202 185 216 186 214 209 207 236 227 236 235 240 218 239 223 223 228 236 1 229 217 235 217 220 218 226 230 231 210 2 229 3 210 4 222 5 221 6 224 7 190 180 186 183 174 176 171 174 175 169 168 164 161 160 160 222 8 169 168 171 175 177 177 178 184 187 188 186 188 192 192 194 197 177 225 217 198 223 157 163 168 165 230 225 205 224 197 197 240 241 223 242 219 222 217 235 211 213 237 202 219 204 9 152 10 233 11 190 12 212 13 189 14 207 193 15 166 160 169 171 167 173 170 178 183 182 185 186 185 189 193 238
3dB Bandwidth, MUX Mode, AV = 2, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 5 OUTPUT CHANNELS 6 7 8 9 10 11 12 13 14 15 295 268 277 279 269 263 259 263 262 253 253 246 241 236 233 227 279 274 244 396 367 407 230 272 412 385 417 411 407 307 308 402 402 387 383 412 412 1 316 290 300 408 391 407 404 398 394 388 2 290 3 397 4 384 5 405 6 395 7 220 211 216 213 201 201 196 201 203 194 194 187 184 182 178 183 8 288 183 192 196 192 196 196 205 212 210 215 213 216 220 220 223 324 276 400 379 413 283 407 411 410 293 412 391 419 396 385 307 300 402 403 387 385 413 415 398 394 298 402 392 289 9 240 10 299 11 250 12 385 13 234 14 396 291 15 188 183 196 196 192 200 200 211 216 214 216 217 225 225 230 293
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FN6251.0 March 21, 2006
ISL59531
3dB Bandwidth, Broadcast Mode, AV = 1, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 5 OUTPUT CHANNELS 6 7 8 9 10 11 12 13 14 15 215 214 210 212 206 203 201 204 204 202 196 194 193 191 189 187 172 173 167 157 155 161 149 170 162 161 170 187 187 182 183 170 172 170 171 175 176 1 198 195 188 178 174 177 156 160 161 157 2 195 3 183 4 184 5 188 6 172 7 178 174 171 171 169 165 163 167 167 164 160 157 156 151 151 153 8 151 152 153 157 157 159 159 167 171 170 169 171 171 174 175 178 167 179 167 160 166 151 156 160 160 169 160 156 164 162 164 168 172 157 160 151 155 158 161 154 159 161 150 143 147 9 145 10 157 11 145 12 140 13 146 14 144 144 15 158 158 159 164 164 164 164 170 175 174 178 174 178 178 178 181
3dB Bandwidth, Broadcast Mode, AV = 2, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 5 OUTPUT CHANNELS 6 7 8 9 10 11 12 13 14 15 234 232 228 229 223 219 217 220 220 218 220 212 211 209 208 205 191 191 184 172 171 176 160 187 179 179 185 204 205 198 199 189 190 190 191 192 193 1 216 215 204 196 193 192 174 175 177 174 2 209 3 199 4 204 5 205 6 190 7 196 193 189 191 186 183 181 183 184 181 176 174 174 170 167 166 8 169 169 171 175 177 177 178 184 187 188 186 188 192 192 194 197 185 195 184 179 185 167 173 178 178 187 177 176 181 181 182 184 188 174 178 169 173 174 178 172 178 177 168 163 164 9 160 10 172 11 162 12 158 13 163 14 161 161 15 178 178 178 182 183 183 183 189 193 193 192 192 195 195 196 198
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FN6251.0 March 21, 2006
ISL59531 Block Diagram
VS+ VOVERn
16 OVERLAY INPUT
OVERn
16 LOGIC CONTROL
VIN0
+
POWER-ON 16 INPUTS
SWITCH MATRIX
16 OUTPUTS
VIN15 REF
+
AV +1, +2 SDI CLK ENA SPI INTERFACE, REGISTER
OUTPUT ENABLE
POWER-ON SDO
General Description
The ISL59531 is a 16x16 integrated video crosspoint switch matrix with differential input and output buffers and OnScreen Display (OSD) insertion. This device operates from a single +5V supply. Any output can be switched to any of the 16 input video signal sources and OSD information through an internal, dedicated fast 2:1 mux located before the output buffer. Also, any one input can be broadcast to all 16 outputs. Each output X is defined as: Voutx = Avx*(INx-INBx+REF) Where Avx = 1, or Avx = 2. Note that all REF's are common between channels and must be externally well buffered and/or bypassed. The ISL59531 offers a -3dB signal bandwidth of 320MHz. The differential gain and differential phase of 0.025% and 0.05 respectively, along with 0.1dB flatness out to 50MHz. The switch matrix configuration and output buffer gain are programmed through an SPI/QSPITM-compatible, three-wire serial interface. The ISL59531 interface is set up to facilitate both fast updates and initialization. On power-up, all facilities are initialized in the disabled state to avoid output conflicts within the user system.
ENA signal. While the ENA is low, the data on the SDI (serial data input) pin is shifted into the 16-bit shift register on the positive edge of the SCLK (serial clock) signal. The LSB (bit 0) is loaded first and the MSB (bit 15) is loaded last (see Table 1). After the full 16-bit data has been loaded, the ENA is pulled high and the addressed output channel is updated. The SCLK is disabled internally when the ENA is high. The SCLK must be low before the ENA is pulled low. The Serial Timing Diagram and parameters table show the timing requirements for three-wire signals.
Digital Interface
The ISL59531 uses a simple 3-wire SPI compliant digital interface to program the outputs. The ISL59531 can support the clock rate up to 5MHz.
Serial Interface
The ISL59531 is programmed through a three-wire serial interface. The start and stop conditions are defined by the
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FN6251.0 March 21, 2006
ISL59531 Serial Timing Diagram
ENA tE
T
tr
tf
tHE
tSE
SCLK tSD tHD tw
SDI
B0 LSB
B1
B2
B12-B2
B14
B15 t MSB
LOAD MSB FIRST, LSB LAST
TABLE 1. SERIAL TIMING PARAMETERS PARAMETER T tHE tSE tHD tSD tW RECOMMENDED OPERATING RANGE 200ns 20ns 20ns 20ns 20ns 0.50 * T Clock Period ENA Hold Time ENA Setup Time Data Hold Time Data Setup Time Clock Pulse Width DESCRIPTION
Programming Model
The device has power-on reset that disables outputs, disables test mode, and turns off analog currents. To start up the device the control word is sent:
TABLE 2. CONTROL WORD FORMAT B15 1 B14 1 B13 1 B12 B11 B10 B9 B8 0 B7 --0 B6 0 B5 0 B4 0 B3 0 B2 0 B1 Power on B0 Common output enable
It is important to always program control bits 2-8 as zeros to avoid activating test modes designed for device manufacturing.The clamp bit activates the input clamp and bleed current sink and works only in the single-ended version. To enable individual outputs, the output enable control word is sent. There are 16 enables to set; this is done with serial words controlling four at a time. The output enable control word format is:
TABLE 3. OUTPUT ENABLE FORMAT B15 0 B14 0 B13 1 B12 B11 B10 B9 N1 B8 N0 B7 B6 On+3 B5 B4 On+2 B3 B2 On+1 B1 B0 On
The Ox bits represent output enables of eight individual registers. The N1 and N0 bits represent a two bit binary number which is used in setting n = 2N1N0. For instance, to access the control bit of the 5th output enable, we send the word:
TABLE 4. OUTPUT ENABLE WORD OF 2ND GROUP OF OUTPUTS B15 0 B14 0 B13 1 B12 B11 B10 B9 0 B8 1 B7 B6 O7 B5
-
B4 O6
B3 -
B2 1
B1 -
B0 O4
Individual output enables are ended with the control register's common output enable bit and the power on bit. 17
FN6251.0 March 21, 2006
ISL59531
Gain Setting The gain of each output may be set to 1 or 2 using the gain set word. It is in the same format as the output enable control word:
TABLE 5. GAIN SET FORMAT B15 0 B14 1 B13 0 B12 B11 B10 B9 N1 B8 N0 B7 B6 Gn+3 B5 B4 Gn+2 B3 B2 Gn+1 B1 B0 Gn
Input to Output Selection Individual outputs receive their input selection choice using the input/output control word. Its format is:
TABLE 6. INPUT/OUTPUT WORD B15 0 B14 0 B13 0 B12 I3 B11 I2 B10 I1 B9 I0 B8 0 B7 B6 B5 B4 O3 B3 O2 B2 O1 B1 O0 B0 0
For a given binarily selected output, as specified by the O's, an input channel is assigned by the binarily selected I's. Sixteen transmissions of the input/output control words will be required to set up all outputs. Note that B8 and B0 must be logic 0. Broadcast Mode The broadcast mode routs one input to all 16 outputs. It has a memory bit that remembers its state. The configuration of input/output assignments that existed before setting broadcast mode is kept in memory and when broadcast mode is disabled the previous configuration is restored. The broadcast control word format is:
TABLE 7. BROADCAST WORD B15 0 B14 1 B13 1 B12 I3 B11 I2 B10 I1 B9 I0 B8 0 B7 B6 B5 B4 B3 B2 B1 B0 EB
EB sets or resets the broadcast mode memory bit. The I's binarily select the input channel to be broadcast to all outputs. Note that B8 must be logic 0.
Bandwidth Considerations
Wide frequency response (high bandwidth) in a video system means better video resolution. Four sets of frequency response curves are shown in Figure 47. Depending on the switch configurations, one can get between 250MHz to 350MHz bandwidth. A short discussion of the trade-offs follows--including matrix configuration, output buffer gain selection, channel selection, and loading.
2
Mux, Av = 2
mode. In addition, output buffer gain of +2 has higher bandwidth than gain of +1 due to internal device compensation. Therefore, the highest bandwidth set-up is multiplexer mode and output buffer gain of +2. The relative location of the input and output channel also has significant impact on the device bandwidth. Again this is due to the layout of the device. When the input and output channels are further away, there are additional parasitics as a result of the distance and lower bandwidth results. The bandwidth does not change significantly with resistive loading as shown in figure 3 in the typical performance curves. However, it does change greatly with capacitance loading, Figure 4 in typical performance curves. This is most significant when laying out the PCB. If the PCB trace between the output of the crosspoint switch and the back termination resistor is not minimized, additional parasitic capacitance severely distorts the frequency response. To emphasize how critical the PCB layout is to performance, let's compare the two boards presented in figures 48 and 49. Figure 48 shows a larger engineering evaluation board where the termination resistor is far away from the device because of the use of a socket. The board in figure 48 is a demoboard without the socket. The parasitic capacitance of the demoboard is about 2.7pF less.
0 Normalized Gain [dB] -2 -4 -6 -8 -10 1 10 100 Frequency [MHz]
Broadcast, Av = 2 Broadcast, Av = 1
Mux, Av = 1
1000
FIGURE 47. FREQUENCY RESPONSE FOR VARIOUS MODES
In multiplexer mode, the input only drives one output channel, while in broadcast mode the same input drives all 16 outputs. The parasitic capacitance of all 16 channels loads down the input and reduces bandwidth in broadcast 18
ISL59531
Linear Operating Region
In addition to bandwidth, one must also be very careful with operating the device at its linear operating region. Figure 50 shows differential gain curve. The ISL59534 is a single supply 5V device with its linear region is between 0.1 and 2V.
FIGURE 48. ENGINEERING EVALUATION BOARD FIGURE 50. DIFFERENTIAL GAIN RESPONSE
Power Dissipation and Thermal Resistance
With a large number of switches, it is possible to exceed the 150C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the crosspoint switch in a safe operating area. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX PD MAX = ------------------------------------------- JA
Where: * TJMAX = Maximum junction temperature = 125C
FIGURE 49. CUSTOMER DEMOBOARD
* TAMAX = Maximum ambient temperature = 85C * JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or:
n
To prove that the parasitic capacitance is the largest contributor to the difference in bandwidth of the two boards, we added 2.7pF at the output of the demoboard. Figure 50 shows the similarity in frequency response of the engineering evaluation board alongside the demoboard piggybacked with 2.7pF.
PD MAX = V S x I SMAX +
i=1
( VS - VOUTi ) x ----------------R Li
V OUTi
19
ISL59531
Where: * VS = Supply voltage = 5V * ISMAX = Maximum quiescent supply current = 375mA * VOUT = Maximum output voltage of the application = 2V * RLOAD = Load resistance tied to ground = 150 * n = 1 to 15 channels
n
PD MAX = V S x I SMAX +
i=1
( VS - VOUTi ) x ----------------- = R Li
V OUTi
2.52W
The reqired JA to dissipate 2.52W is:
T JMAX - T AMAX JA = -------------------------------------------- = 15.9 ( C/W ) PD MAX
Table 8 shows JA thermal resistance results for various airflows. At the thermal resistance equation shows, the required thermal resistance depends on the maximum ambient temperature.
TABLE 8. JA THERMAL RESISTANCE [C/W] Airflow [LFM] 0 18 250 14.3 500 13.0 750 12.6
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 20
356 Ld PBGA Package
21
ISL59531

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